Channel Dependency Graph is a directed graph of a network that captures all of the dependencies. A network is deadlock free if the CDG is acyclic.
Channel
A set of wires that carry a particular type of data.
Channel Dependency Graph
A directed graph of all the dependencies in the network. A network is said to be deadlock free if its CDG is acyclic.
CHI
Coherent Hub Interface is an AMBA interface specification for connection of fully coherent processors and dynamic memory controllers to high performance non-blocking interconnects.
Clock Domain
A set of components that share the same clock source.
Cluster
A grouping construct instantiated as part of a larger interconnect. A cluster has a protocol boundary that is intended to be connected to other clusters. A cluster is typically used for a subsystem or chiplet.
Component
A module that is part of the NoC. Usually a router or bridge, but sometimes an in-link module.
CSR
Configuration and Status Register is a register that is used to configure and provide status of the fabric and its components.
CXL
Compute Express Link is an open standard interconnect for high-speed, high capacity CPU-to-device and CPU-to-memory connections, designed for high performance data center computers.