Products
Software-Defined Fabric IP for Scalable SoCs, Chiplets, and AI infrastructure
WeaveIP is an advanced system IP portfolio for building unified, software-defined fabrics across complex SoCs and chiplet-based architectures. Built on a common scalable transport architecture, WeaveIP enables design teams to connect CPUs, accelerators, memory, I/O, coherent clusters, custom agents, and chiplets with the flexibility required for next-generation AI, datacenter, infrastructure, automotive, and IoT systems.
Built on a common scalable transport architecture, WeaveIP enables design teams to build coherent, non-coherent, and custom protocol fabrics with the topological flexibility required for complex SoCs and chiplet-based systems. The portfolio helps connect CPUs, accelerators, memory, I/O, coherent clusters, custom agents, and chiplets while optimizing for maximum performance, scale, bandwidth, latency, power, area, QoS, RAS, and physical implementation.
With WeaveIP, design teams can configure the fabric to match system requirements, optimize for bandwidth, latency, power, area, QoS, RAS, and physical implementation, and accelerate the path from architecture to deployable RTL.
High-bandwidth, low-latency fabric IP for complex SoCs and multi-chiplet systems.
Build fabrics for AMBA, CHI, AXI, custom protocols, and chiplet-ready architectures.
Use a common scalable transport to support multiple protocols with greater efficiency.
Configure fabrics around system architecture, workload needs, and physical layout requirements.
Support predictable performance, reliability, debug, and post-silicon insight across complex systems.
Enable tile-friendly, modular designs that simplify scaling, integration, and implementation.
Chiplet-ready, protocol-neutral Network-on-Chip soft IP designed for AI and heterogeneous compute systems that require extreme bandwidth, low latency, flexible topology, and custom protocol support. It enables transport for customer-defined message-passing protocols, with support for tiling, QoS, clusters, AI-focused multicast/scatter-gather features, and shared transport with AMBA protocols and multi-chiplet connectivity through UCIe FDI
Configurable AMBA-based non-coherent fabric for high-performance SoCs and multi-chiplet designs. It natively connects a wide range of AXI, APB, ACE-Lite, and AXI-Lite non-coherent interfaces, with efficient PCIe, DDR, and HBM connectivity to help teams build high-bandwidth, low-latency fabrics with flexible topology control, QoS, RAS, and physical implementation support.
Configurable cache-coherent fabric designed to scale across large SoCs and multi-chiplet systems. It supports CHI, ACE-Lite, AXI-Lite, UCIe FDI, PCIe, and HBM interfaces, enabling high-bandwidth, low-latency coherent communication with advanced topology flexibility, full cache coherency features, built-in system-level cache, QoS, and RAS.
Extreme port-density, non-blocking, multi-chiplet switch fabric for AI scale-up and scale-out systems. NeuraScale supports large numbers of UALink™, Ultra Ethernet, UCIe, and AMBA ports while maintaining low latency, robust bandwidth, and a tile-friendly physical design for scalable chiplet-based architectures.
Industry’s first multi-level cache coherent fabric IP, designed for large coherent clusters and chiplet-scale compute systems. It enables design teams to scale coherency across CPUs, accelerators, memory subsystems, and chiplets while maintaining performance, configurability, and efficient system-level data movement.
WeaveIP includes configurable cache controller capabilities for systems that require optimized memory access, cache hierarchy flexibility, and coherent data sharing. The cache controller can support a range of configurations and features, including system-level cache capabilities, QoS, RAS, and performance tuning for complex compute platforms.
Built-in QoS, congestion isolation, and physically-aware tiling deliver predictable tail latency — even under mixed workload pressure.
Built-in QoS, congestion isolation, and physically-aware tiling deliver predictable tail latency — even under mixed workload pressure.
Built-in QoS, congestion isolation, and physically-aware tiling deliver predictable tail latency — even under mixed workload pressure.
Featured Case Study
Tenstorrent collaborated with Baya Systems to advance its AI fabric architecture using WeaveIP™ fabric IP and the WeaverPro™ software platform. The result was a measurable uplift in performance, efficiency, and scalability for next-generation AI systems, while reducing silicon footprint and improving the fabric’s ability to support future chiplet-ready architectures.
Improved fabric performance for demanding AI workloads.
Reduced latency at prior-generation peak bandwidth.
Smaller fabric footprint while improving overall efficiency.
Resources
Baya Systems and Aion Silicon Partner to Accelerate Next-Generation SoC and Chiplet Designs
Baya Systems & Tenstorrent Showcase Optimized Subsystem for TT-Ascalon™ Processors
WeaveIP is a portfolio of products built on a common transport that is architected for efficiency and allows for creation of unified fabric solutions that are optimized for minimum power and silicon footprint without compromising performance, and deployed faster with clarity on achieving KPI targets
White paper
This whitepaper covers how Tenstorrent is elevating their already industry-leading AI fabric to new heights of performance, efficiency, and productivity through a collaboration with Baya Systems. Tenstorrent’s in-house fabric has set a new standard for efficiency and performance in AI compute in their current generation products and is proactively addressing the needs of the next generation. By combining Tenstorrent’s proven AI system architecture with Baya Systems’ WeaveIP™ fabrics and WeaverPro™ software platform, the new AI fabric is able to deliver significant improvements across all key performance metrics while also reducing the total fabric silicon footprint and power consumption. Such results are unmatched by any in-house or off-the-shelf fabric solution and is propelling the next Tenstorrent AI products to a stratospheric level of efficiency and scaling.
Equally transformative is the shift in the development process to improve Tenstorrent’s time to market (TTM), enhance customer total cost of ownership (TCO) and establish a future-proof, chiplet-ready fabric architecture that can scale seamlessly with the demands of large AI models and new workloads.
CacheStudio is a rapid architecture and design platform for chiplet based cache coherent systems. Cache hierarchies and parameters are specified in minutes with an abstract Python frontend, and accurate workload driven simulations are performed at Millions of instructions per second to uncover stateful performance indicators that require long runtimes. The results are presented interactively at multiple abstraction levels and organized structurally with the cache hierarchy and the chiplet organization, for intuitive comprehension and analysis.
