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Flexible, High-Performance Connectivity for Advanced SoCs and Chiplet Systems
Modern SoCs and chiplet-based systems require flexible, high-performance fabrics that can efficiently connect a wide variety of non-coherent interfaces, memory, I/O, accelerators, and die-to-die links. As bandwidth, latency, and physical implementation requirements become more complex, fabric design must be optimized around real system KPIs rather than guesswork.
Baya’s Configurable AMBA Non-Coherent Fabric IP provides a flexible Network-on-Chip IP for high-performance SoCs and multi-chiplet designs, delivering high bandwidth, low latency, and built-in QoS and RAS. It natively connects AXI, APB, AXI-Lite, ACE-Lite, PCIe, HBM, DDR, and UCIe FDI interfaces through Baya’s scalable transport architecture.
Configured and optimized through FabricStudio, the fabric enables teams to explore topology, hierarchy, traffic patterns, and physical design constraints to meet bandwidth and latency targets while minimizing area and implementation risk. With support for advanced tiling, multicast, performance monitoring, and programmable QoS, it helps engineering teams build efficient, physically realizable non-coherent interconnects for scalable compute systems.
Connect a wide range of AXI, APB, AXI-Lite, and ACE-Lite interfaces across CPUs, accelerators, PCIe controllers, memory controllers, coherent fabrics, and address-mapped peripherals.
Enable efficient connectivity to PCIe, DDR, HBM, and UCIe-based die-to-die links with support for wide interfaces, multiple memory channels, and scalable high-throughput data movement.
Scale across up to 256 chiplets with flexible topology control, adaptive three-dimensional routing, and full topology customization through FabricStudio.
Use programmable bandwidth allocation, flow priority, route selection, input rate limiting, latency monitoring, and automatic QoS regulation to meet system-level performance goals.
Reduce implementation risk with advanced tiling, hierarchical design generation, RAS, debug, trace, performance monitoring, and PPA optimizations for scalable physical implementation.
Discover how Baya’s configurable non-coherent fabric helps teams connect AXI/APB interfaces, memory, I/O, and accelerators with high bandwidth, low latency, and implementation-ready flexibility. Connect with our team to discuss your architecture goals.
Explore the capabilities of Baya’s configurable non-coherent fabric for high-performance SoCs and multi-chiplet designs. The brief outlines its supported protocols and interfaces, topology and tiling flexibility, scalability, multicast and address-mapping features, bandwidth and latency management, QoS controls, performance monitoring, RAS, security, and power-performance-area optimizations.