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Scalable Coherent Connectivity for Advanced SoCs and Chiplet Systems
Advanced SoCs and chiplet-based systems need coherent fabrics that can efficiently connect CPUs, accelerators, memory, I/O, and peer-to-peer traffic while maintaining data consistency across the system. As coherent traffic scales across more agents, memories, and chiplets, the fabric must balance bandwidth, latency, cache coherency, QoS, and physical implementation requirements.
Baya’s Configurable Cache Coherent Fabric IP provides a scalable Network-on-Chip for systems where major traffic is coherent. It supports AMBA CHI interfaces for fully coherent agents, AXI interfaces for non-coherent and I/O-coherent agents, and ACE-Lite connectivity for I/O-coherent devices, enabling coherent, non-coherent, and peer-to-peer traffic to share a unified fabric architecture.
Configured and optimized through FabricStudio, the fabric gives teams flexible topology control, cache coherence controllers, built-in system-level cache, QoS, RAS, and physically aware implementation capabilities. It helps engineering teams build high-bandwidth, low-latency coherent interconnects that scale across advanced SoCs and multi-chiplet systems while reducing design risk and accelerating time to market.
Build cache-coherent fabrics across large SoCs and multi-chiplet systems with support for up to 256 chiplets, 128 HN slices, and flexible coherent topology control.
Connect fully coherent CHI agents, AXI-based system IP and memory controllers, ACE-Lite I/O-coherent devices, PCIe controllers, and non-coherent fabric through a unified system fabric.
Support up to 512 MB of system-level cache, configurable snoop filters, UMA/NUMA/sub-NUMA modes, atomics, cache maintenance operations, and advanced coherency features.
Use weighted bandwidth allocation, flow priority, virtual channel isolation, route selection, input rate limiting, and bandwidth/latency monitoring to meet system-level performance targets.
Enable modular implementation with advanced tiling, hierarchical design generation, RAS, debug, trace, ECC protection, runtime repair, and PPA optimizations for scalable physical design.
Discover how Baya’s coherent fabric helps teams connect CPUs, accelerators, memory, I/O, and chiplet-based systems with scalable cache coherency, high bandwidth, and implementation-ready flexibility. Connect with our team to discuss your architecture goals.
Learn how Baya’s coherent fabric supports large SoC and multi-chiplet systems with scalable cache coherency, configurable system-level cache, high-bandwidth connectivity, and low-latency data movement. The brief highlights supported protocols and interfaces, topology and tiling options, address mapping, bandwidth allocation, QoS, performance monitoring, RAS, security, and power-performance-area optimizations.