Powering the Silicon Shaping Every Modern Industry

As demand grows for scalable, efficient, and customized compute, more companies are turning to RISC-V as the preferred architecture for high-performance computing. Tenstorrent and Baya Systems have designed a compute subsystem combining IP from both companies designed to enable AI and HPC use cases. The solution leverages Tenstorrent’s Ascalon™ processor and Baya’s advanced interconnect technology. This paper showcases a compute subsystem that has been designed to deliver strong performance, power efficiency, flexibility and scalability, making it suitable for cloud, server, data center, and edge computing applications to be used in SoCs and chiplets. This collaboration also enables rapid customization and extension of well-tested compute subsystems.

This whitepaper covers how Tenstorrent is elevating their already industry-leading AI fabric to new heights of performance, efficiency, and productivity through a collaboration with Baya Systems. Tenstorrent’s in-house fabric has set a new standard for efficiency and performance in AI compute in their current generation products and is proactively addressing the needs of the next generation. By combining Tenstorrent’s proven AI system architecture with Baya Systems’ WeaveIP™ fabrics and WeaverPro™ software platform, the new AI fabric is able to deliver significant improvements across all key performance metrics while also reducing the total fabric silicon footprint and power consumption. Such results are unmatched by any in-house or off-the-shelf fabric solution and is propelling the next Tenstorrent AI products to a stratospheric level of efficiency and scaling.

Equally transformative is the shift in the development process to improve Tenstorrent’s time to market (TTM), enhance customer total cost of ownership (TCO) and establish a future-proof, chiplet-ready fabric architecture that can scale seamlessly with the demands of large AI models and new workloads.

CacheStudio is a rapid architecture and design platform for chiplet based cache coherent systems. Cache hierarchies and parameters are specified in minutes with an abstract Python frontend, and accurate workload driven simulations are performed at Millions of instructions per second to uncover stateful performance indicators that require long runtimes. The results are presented interactively at multiple abstraction levels and organized structurally with the cache hierarchy and the chiplet organization, for intuitive comprehension and analysis.

The future of AI-driven compute depends on how well data can move. Traditional network-on-chip (NoC) architectures are hitting their limits, and the next generation of RISC-V subsystems demands faster, more intelligent interconnects.

In this live engineer-focused session, Baya Systems and Tenstorrent will explore why collaboration between compute and fabric IP is now critical for performance and scalability in modern SoC design. You’ll see how combining Ascalon processors and Tenstorrent System IP with Baya’s RISC-V Fabric IP enables more efficient data movement, stronger interoperability, and streamlined subsystem integration.

The session will include a live interoperability demo showing the Ascalon + Baya Fabric IP reference design in action.

What You’ll Learn