Technology
Baya helps semiconductor teams design, optimize, and deploy high-performance data movement fabrics across compute, memory, I/O, and chiplets. Smart, customizable system IP solutions that drive unmatched efficiency and scale for SoCs and chiplets. Eliminate guesswork, slash risks, and cut costs while delivering high-performance systems.
Hyper-efficient transport fabric that can deliver 4 TB/s throughput in a single cluster, and scale to multiple PB/s for multi-chiplet AI applications, and support advanced high-bandwidth memories
The fabric is extremely flexible and can be customized to any topology. It can be extended to custom protocols for innovation in quality-of-service (QoS), debug and more.
Transport is separate from protocol layers, minimizing wires and logic in building a unified fabric that supports coherent, non-coherent, and custom protocols for greatest efficiency with lowest cost and power.
Extensive analysis and optimization through software platform enables a fabric that delivers guaranteed performance on target workloads and can be algorithmically optimized for future workloads.
Software-driven development ensures the fabric is correct by construction, and deadlock free with traditional and formal validation, substantially reducing risk for system development.
The fabric is developed with modular components, improving flexibility and expediting design delivery. It uses physical-design-aware tiling approaches to ease implementation, integration and signoff.
• Verifiable protocol-level cluster perimeter
• Performance and congestion isolation
Multi-level cache coherent fabric IP and supports UMA, NUMA or sub-NUMA
• Co-optimization of cache, memory, IO stacks
• Data-driven D2D analysis and optimization
Our unified fabric provides a common transport supporting multiple protocols and coherency needs within a unified design flow. Physically-aware solutions can be optimized for power and area while delivering unprecedented performance, low latency and other key performance indicators (KPIs) from concept to deployment.
Support for QoS
and RAS
Extensive flexibility in topologies and scale
Correct by construction
and deadlock free
Common transport optimizes performance and area
Fabric channels in high performance silicon can take up to 20% of die area and power consumption
Up to 2x smaller fabric
vs standard mesh iso-performance
Performance bottlenecks created by protocol bridges, fabric transit points, and longer routes
Up to 3 GHz and 32 PB/s
bisection bandwidth
Need for numerous protocol crossing bridges and scenic routes for communication flows
Lower latency system
and workload dependent
Deadlocks, QoS and tradeoffs unclear during design development
Up to 8 virtual channels per network, deadlock-free, QoS built-in
Limited number of topologies, performance not scalable
8b-2048b channel width with wide
variety of topologies
Performance issues slow down architecture, complexity challenges slow down implementation
Data-driven design and physically-aware implementation