About
Who we are
Baya Systems delivers unified, software-defined fabric solutions that enable efficient and scalable data movement across heterogeneous chiplet architectures. As AI infrastructure grows increasingly complex, traditional interconnect approaches struggle to meet the demands of bandwidth, latency, scalability, and power efficiency. Baya addresses these challenges with intelligent fabric technology designed to simplify connectivity between compute, memory, and accelerator components.
Its architecture empowers semiconductor teams to optimize performance, reduce integration complexity, and accelerate system-level innovation for AI accelerators, data centers, automotive platforms, and high-performance computing systems. By combining configurable software-driven infrastructure with advanced fabric IP, Baya helps organizations shorten development cycles, improve architectural flexibility, and reduce implementation risk.
Founded
Countries Worldwide
Awards and Recognitions
Engineers & Experts
What we do
The rapid advancement of AI and high-performance computing is driving demand for sophisticated platforms that integrate CPUs, GPUs, accelerators, memory, and communication components. These systems face growing challenges in scalability, data movement, power efficiency, cost, and software complexity.
Chiplet-based architectures offer a promising solution by enabling modular, reusable, and composable system design. However, they also introduce new integration and interconnect challenges that require intelligent, scalable fabric solutions to unlock their full potential.
Baya Systems is inspired by the baya weaver, a bird renowned for weaving intricate, lightweight, yet robust nests, from diverse materials with remarkable efficiency.
Scalable solutions for AI systems
Intelligent fabrics powering connectivity
Recognized innovation across semiconductor industry
What we do
Taming the complexity of next-generation design
The rapid advancement of AI and high-performance computing is driving demand for sophisticated platforms that integrate CPUs, GPUs, accelerators, memory, and communication components. These systems face growing challenges in scalability, data movement, power efficiency, cost, and software complexity.
Chiplet-based architectures offer a promising solution by enabling modular, reusable, and composable system design. However, they also introduce new integration and interconnect challenges that require intelligent, scalable fabric solutions to unlock their full potential.
Baya Systems is inspired by the baya weaver, a bird renowned for weaving intricate, lightweight, yet robust nests, from diverse materials with remarkable efficiency.
Taming the complexity of next-generation design
The rapid advancement of AI and high-performance computing is driving demand for sophisticated platforms that integrate CPUs, GPUs, accelerators, memory, and communication components. These systems face growing challenges in scalability, data movement, power efficiency, cost, and software complexity.
Chiplet-based architectures offer a promising solution by enabling modular, reusable, and composable system design. However, they also introduce new integration and interconnect challenges that require intelligent, scalable fabric solutions to unlock their full potential.
Baya Systems is inspired by the baya weaver, a bird renowned for weaving intricate, lightweight, yet robust nests, from diverse materials with remarkable efficiency.
Scalable solutions for AI systems
Intelligent fabrics powering connectivity
Recognized innovation across semiconductor industry
Partner Ecosystem
Dr. Sailesh Kumar is a seasoned expert in SoC, Fabric, IO, Memory architecture, and algorithms, with over two decades of experience. He has pioneered several high-impact, industry-first technologies, including 400G Network Processor at Huawei, Software Defined Fabric at NetSpeed, Xeon Architecture Transportation at Intel, and Software Defined Chiplet at Baya. Sailesh founded NetSpeed Systems and served as its Chief Technology Officer until its successful acquisition by Intel. At Intel, as a Fellow, he initiated and led multiple projects, such as the design of a Xeon platform automation system and the standardization of data center compute protocols. Sailesh is also a prolific author, with more than two dozen highly cited papers and over 150 patents. He holds a PhD from Washington University in St. Louis and a B.Tech. from the Indian Institute of Technology Kanpur.
Nandan Nayampally is a semiconductor executive with nearly three decades of experience in engineering, product and business roles. With an extensive background in processing, systems and software and in particular IP, after an initial start on Athlon processor team at AMD, he spent 16 years at Arm building the processor, fabric, vertical product businesses, and was General Manager for the CPU business and first GM of the Client business. He led Amazon’s 3rd party Alexa effort, and had key roles at Denali, and most recently at BrainChip, focusing on bringing disruptive technologies to market.
Nandan has an M.A. in Computer Science from University of Texas, Austin, and a B.Tech. from the Indian Institute of Technology, Mumbai.
Dr. Eric Norige is a software expert with over three decades of programming experience in a wide variety of contexts. In the last decade, he has found a niche in the Network-on-Chip space, being an early employee at Netspeed Systems and via acquisition inside Intel as a Principal Engineer. Eric has a Ph.D. in Computer Engineering from Michigan State University and a BA+BS in Math/Computer Science from Truman State University.
Dr. James Aldis has been working in on-die and inter-die networking since the early 2000s, for Texas Instruments, Imagination Technologies, Intel Corporation and others. He has built chips using all the important independent NoC technologies of the last 20 years as well as many proprietary interconnect technologies. Additionally, he has made many contributions to industry ecosystem development in the areas of SystemC-TLM, OCP-IP, AMBA and HSA. James has a PhD in electronic engineering from the University of York and a BSc in pure mathematics from the University of Liverpool.
Joji Philip is a seasoned hardware engineering leader with over two decades of experience in developing and productizing HW IPs. As a founding engineer at NetSpeed Systems, he played a crucial role in pioneering innovations in coherent and non-coherent NoC interconnects and memory subsystems. Joji’s expertise spans interconnects, cache coherency, NoC, SoCs, memory subsystems, PCIe, high-speed interfaces, network processors, and low-power designs. He has held key positions at Intel, Huawei Technologies, Qualcomm, and Conexant, where he drove the development and implementation of new technologies and products. As part of the founding team at Baya, he has been instrumental in building and leading HW design and verification teams across the US and India. Joji holds a Master of Science in Computer Engineering from the New Jersey Institute of Technology and a Bachelor of Engineering in Electronics Engineering from the University of Pune.
Nishant Rao is a seasoned technologist and leader with over a decade of experience in software development, specializing in network-on-chip (NoC) technology, cache coherency, and SoC integration. At Baya Systems, Nishant is responsible for the global development, verification, and deployment of the WeaverPro Software Platform. Nishant began his career at NetSpeed Systems, where he was responsible for several aspects of the software infrastructure including algorithmic NoC construction and cache coherency. He then served as the Software Lead for Configurable Fabrics at Intel, a role that deepened his expertise in NoC design and SoC architecture. Nishant has made significant contributions to the fields of machine learning for NoC design and SoC design automation, that have resulted in at least 13 patents to date. Nishant has an MS in Computer Engineering from Georgia Tech and a B.Tech in Electronics Engineering from VJTI, Mumbai.
Kent Orthner has over 25 years of experience designing all aspects of on-chip networks, FPGA technology, and high-speed silicon connectivity. Before joining Baya Systems, Kent served as Sr. VP of Engineering at Achronix Semiconductor, where he led the development of cutting-edge FPGA devices and IP solutions, including the FPGA-embedded high performance on-chip network. Before Achronix, Kent served as the Vice President of Engineering at Arteris, where he was responsible for all hardware and software development, and where he developed and released the world’s first highly scalable and configurable cache-coherent interconnect IP. Before that, Kent spent 11 years at Altera, leading multiple cross-functional engineering teams, including Altera's NoC design tool suite, IP infrastructure, and debug and design visibility tools. Kent holds a Master of Engineering in Electrical Engineering from Carleton University, Canada, and a Bachelor of Applied Science in Computer Engineering from the University of Ottawa, Canada.
Jim Keller is a veteran hardware engineer and an authority in advanced processing systems. He is currently the CEO of Tenstorrent. Prior to joining Tenstorrent, he served as Senior Vice President of Intel’s Silicon Engineering Group. He has held roles as Tesla’s Vice President of Autopilot and Low Voltage Hardware, Corporate Vice President and Chief Cores Architect at AMD, and Vice President of Engineering and Chief Architect at P.A. Semi, which was acquired by Apple Inc. Jim has led multiple successful silicon designs over the decades, from the DEC Alpha processors, to AMD K7/K8/K12, HyperTransport and the AMD Zen family, the Apple A4/A5 processors, and Tesla’s self-driving car chip. Jim holds a Bachelor of Engineering from Penn State University.
Stan Reiss is a partner at Matrix, where he has been backing early-stage technology companies for over two decades. In addition to Baya, his semiconductor investments include Acacia Communications, Nubis, and Lightmatter. Stan has a B.S. in Electrical Engineering from Cornell University, M.S. degrees in Electrical Engineering and Operations Research from the Massachusetts Institute of Technology, and an MBA from Harvard Business School.
Siva K. Yerramilli is Senior VP of Strategic Programs at Synopsys and leads Corporate Incubation Group (CIG). Siva is responsible for driving the incubation of bold new ideas that can result in big-step innovation, especially cross-domain initiatives. Some of the previous initiatives that have graduated from incubation to productization have included design technology co-optimization (DTCO) and many other initiatives. Siva joined Synopsys in 2019, prior to which, Siva held several technical and management positions across various aspects of technology development/enablement, silicon product development and Intel Custom Foundry at Intel. He has more than 37 years of experience in the semiconductor industry.
Siva has a bachelor’s in electronics and telecommunications from Jawaharlal Nehru Technological University, India. A master’s in computer engineering from Syracuse University and has completed the Executive Management Program at Harvard University.
Manish Muthal is a Sr. Managing Director at Maverick Silicon. Prior to joining Maverick, Manish was a Senior Vice President for Hyperscaler engagements at KIOXIA. He has served in executive roles at semiconductor companies such as Intel, Xilinx, Broadcom, and LSI, where he built and led organizations that delivered record revenue growth. He has also co-founded multiple venture backed start-ups, and has been a corporate investor, sponsor, and board advisor at multiple successful companies at their earliest stages.
He received his B.S. from Visvesvaraya National Institute of Technology Nagpur, India, and his M.S. in Computer Engineering from the University of California Santa Barbara.
