Joint solution reduces risk and accelerates time-to-silicon for advanced semiconductor platforms
Award highlights collaboration driving RISC-V processor-based AI systems and chiplet adoption
Santa Clara, Calif. – October 22, 2025 — Baya Systems, a pioneer in software-driven, chiplet-ready semiconductor fabric IP for scalable AI and high-performance computing, and Andes Technology, a leading supplier of high-performance, low-power RISC-V processor IP, today announced that Baya has been named Andes’ 2025 Partner of the Year. The award recognizes Baya and Andes’ joint efforts to advance next-generation coherent compute systems across datacenter, automotive, and infrastructure markets, showcasing how ecosystem collaboration accelerates RISC-V and chiplet adoption. “The era of siloed innovation is over. Meeting the demands of AI and high-performance computing requires deep collaboration,” said Dr. Sailesh Kumar, CEO and Founder of Baya Systems. “Our partnership with Andes represents that shift: open, scalable, and ecosystem driven. We’re honored to be named Andes’ Partner of the Year and energized by what’s ahead.”
Partnership Results
Bayaand Andes’ partnership has showcased how Baya’s system design approach enables rapid development of RISC-V core-based systems. Next, the companies are creating a reference system integration of Andes’ recently announced flagship high-performance RISC-V processor, “Cuzco,” developed by Andes’ US subsidiary, Condor Computing. Using Baya’s WeaveIP™ smart fabric and WeaverPro™ software-driven system design platform with Andes’ industry-leading RISC-V processor IP, semiconductor architects can analyze, optimize and scale complex SoCs and chiplet-based systems more efficiently.
The collaboration shortens time to market, accelerates design closure and reduces development risk, all while enhancing performance and efficiency. Baya’s unique unified transport enables the creation of tightly coupled high-performance systems combining different protocols and advanced AI fabric. Together, Baya’s physically-aware interconnect technology and Andes’ high-efficiency RISC-V cores provide exceptional performance-per-watt, especially critical for power-constrained datacenter and edge applications.
“Andes and Baya share a vision of accelerating high-performance SoC innovation through open and interoperable design platforms,” said Dr. Charlie Hong-Men Su, President and CTO of Andes Technology. “By combining RISC-V performance leadership with Baya’s advanced interconnect and system design platform, we’re enabling flexible, future-ready systems that can scale with the industry’s most demanding workloads.” Dr. Su presented Dr. Kumar with the Partner of the Year award at Baya’s headquarters.
Exhibition and Demo
Over the past year, the companies have co-hosted technical workshops and ecosystem showcases, often including partners specializing in compute, interconnect and memory, such as Imagination Technologies. These sessions highlight real-world implementations where software-defined fabrics and open RISC-V compute architectures deliver faster, more scalable innovation.
At the RISC-V Summit North America 2025 (October 22–23), Baya Systems is showcasing live demos of its Andes collaboration at the Andes booth (#P6).
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