glossary

Explore our glossary of terms related to our target markets , applications and technologies

A

AMBA

Advanced Microcontroller Bus Architecture is an open-standard that outlines how to connect and manage the different components or blocks within system-on-a chip (SoC) designs. AMBA has evolved over several years to include multiple versions of specifications. 

AXI

Advanced eXtensible Interface is an AMBA interface specification targeted at high performance, high clock frequency system designs.

B

Backpressure

A condition where a channel is unable to accept new data, usually because its buffer is full.

Bridge

A module that connects a host to the network.

C

CDG

Channel Dependency Graph is a directed graph of a network that captures all of the dependencies. A network is deadlock free if the CDG is acyclic.

Channel

A set of wires that carry a particular type of data.

Channel Dependency Graph

A directed graph of all the dependencies in the network. A network is said to be deadlock free if its CDG is acyclic.

CHI

Coherent Hub Interface is an AMBA interface specification for connection of fully coherent processors and dynamic memory controllers to high performance non-blocking interconnects.

Clock Domain

A set of components that share the same clock source.

Cluster

A grouping construct instantiated as part of a larger interconnect. A cluster has a protocol boundary that is intended to be connected to other clusters.  A cluster is typically used for a subsystem or chiplet.

Component

A module that is part of the NoC. Usually a router or bridge, but sometimes an in-link module.

CSR

Configuration and Status Register is a register that is used to configure and provide status of the fabric and its components.

CXL

Compute Express Link is an open standard interconnect for high-speed, high capacity CPU-to-device and CPU-to-memory connections, designed for high performance data center computers.

D

Deadlock

A condition where backpressure has propagated in a cycle, becoming self-sustaining.

Domain Crosser

A module that adapts between two clock domains.

E

EOP

End of Packet is the last flit of piece of data in a packet.

F

Fabric

Interconnect infrastructure that facilitates communication between various components, such as cores, memory, peripherals, or chiplets, within a chip or across multiple chips. It is a high-speed, scalable network-like structure designed to manage data transfer, ensuring efficient, low-latency, and high-bandwidth communication.

Flit

A unit of data that is sent through the network. Short for Flow Control Unit.

Flow

The unit of mapping of traffic to the network. A flow is the set of all possible flits that are sent from one source to one destination.

H

Hierarchy

The pattern of designs that are instantiated into the fabric such as a flat or mapped pattern to match a pattern of physical reuse.

Home Node

Manages the coherent part of the system address space.  It takes in requests from the Request Nodes, handle snoops, communicates with the cache and DRAM, and handles responses and acknowledgements. 

Hop

One or more links that form a connection between a router/bridge and another router/bridge.

Host

A module that connects to the network through a bridge.

I

Interface

A set of channels that are used together to send and receive data.

K

KPI

Key Performance Indicator. A measurable metric used to evaluate the success, efficiency, or quality of the design process, performance, or output.

L

M

Mesh

Fabric topology where each node (e.g., processor, memory, or IP core) is connected to its immediate neighbors in a grid-like pattern, typically forming a 2D rectangular or square lattice. Each node communicates directly with adjacent nodes (north, south, east, west) via dedicated links, enabling scalable, regular, and efficient data routing.

Multicast

Write transaction sent by a single initiator is replicated by the network so it can be received at multiple targets. 

N

NoC

Network-on-Chip. A router-based packet switching network between SoC modules.

NoCTop

A Sub-NoC that forms the top-level design of a NoC, has no ports available to connect to other NoCs.

P

Packet

A set of flits that are sent together from one source to one destination. Packets are required to be transmitted non-interleaved and will be delivered non-interleaved.

PMON

Performance Monitoring counters provide extensive insights into router events and metrics to support performance analysis, debugging,  and post-silicon tuning of a fabric.

Protocol

A set of rules that determines how data is sent and received over a network.

Q

QoS

Quality-of-Service. It refers to the performance level and reliability of a system, network, or service, measured by specific metrics to ensure it meets user or application requirements.

R

RAS

Reliability, Availability, and Serviceability in data centers refers to a set of design principles and metrics ensuring systems operate reliably, remain available for use, and are easy to maintain or repair.

Request Node

Block that is a traffic source that produces and pasess on requests to Home Nodes.

Router

A module that routes flits from input ports to output ports.

RSN

Router Switch Network is the name of a Baya System's router module.

RTL

Register Transfer Language is a low-level language used to describe the functioning of a digital circuit, specifically the transfer of information between registers.

S

SoC

System-on-Chip. A chip that integrates an entire system onto it.

SOP

Start of Packet is the first flit or piece of data in a packet.

Sub-NoC

A grouping construct, able to have both transport links and protocol links on its boundary, intended for hierarchical construction of larger fabrics and design reuse within a single NoC.

T

Topology

The pattern of connectivity between a fabric's components such as a mesh, tree, ring or partial grid.

Transport

The functionality provided by the routers within a NoC: getting packets from one place to another.

TRM

Technical Reference Manual is a document that provides detailed information about the technical specifications, functionality, and operational procedures of a product or system.

V

VC 

Virtual Channel is logical channel that allows a single physical channel to have independent backpressure for different packets. They allow separate flow control for different messages without requiring additional physical wires. 

Virtual Channel

Virtual Channel is logical channel that allows a single physical channel to have independent backpressure for different packets. They allow separate flow control for different messages without requiring additional physical wires. 

VPS

Virtualized Packet Streaming is a simple transport protocol that allows for single or multi-flit packet transmission.  It makes a good foundation layer for other protocols to be transported over.

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