Baya Systems Semicon Tantra 2025

From Bottleneck to Breakthrough: Baya’s Scalable Fabric for High-Bandwidth AI and HPC Silicon

As compute density and heterogeneity grow rapidly in modern SoCs targeting high-performance computing (HPC) and artificial intelligence (AI) workloads, efficient data movement has emerged as a critical performance and power bottleneck. With increasing core counts, high-speed accelerators, and complex memory hierarchies, traditional bus and crossbar-based interconnects fail to scale, resulting in congestion, latency variability, and unsustainable energy costs. In this presentation, we analyze the systemic limitations of conventional interconnect architectures in high-bandwidth scenarios and highlight how these limitations impact overall system efficiency, particularly in AI workloads with irregular and bandwidth-intensive communication patterns.

 

We then explore the role of advanced Network-on-Chip (NoC) architectures in overcoming these challenges. Drawing on real-world design insights from leading-edge NoC IP developed at Baya Systems, we present key architectural considerations that enable scalable, low-latency, and power-efficient data movement. We also introduce configurable NoC design techniques optimized for the heterogeneous and high throughput demands of modern SoCs. This presentation aims to provide chip architects and system designers with practical guidance and innovation strategies to tackle the growing data movement crisis in next-generation HPC and AI silicon.