The future of AI-driven compute depends on how well data can move. Traditional network-on-chip (NoC) architectures are hitting their limits, and the next generation of RISC-V subsystems demands faster, more intelligent interconnects. 

In this live engineer-focused session, Baya Systems and Tenstorrent will explore why collaboration between compute and fabric IP is now critical for performance and scalability in modern SoC design. You’ll see how combining Ascalon processors and Tenstorrent System IP with Baya’s RISC-V Fabric IP enables more efficient data movement, stronger interoperability, and streamlined subsystem integration. 

The session will include a live interoperability demo showing the Ascalon + Baya Fabric IP reference design in action.

What You’ll Learn

• Why traditional NoCs struggle to meet modern AI and HPC demands

• How RISC-V subsystems are evolving to improve on-chip data transfer

• The importance of interoperability across IP providers

• How Baya’s Fabric IP complements Tenstorrent compute and system IP

• Practical steps from a real reference design and integration example

Panelists

• Luke Yen: Fellow at Tenstorrent leading performance modelling and optimisation for high-performance RISC-V CPUs, ML chips, and chiplet SiPs. Previously led performance teams at Meta Reality Labs and Qualcomm, with micro-architecture work at AMD.

• Kent Orthner: Veteran silicon engineer at Baya Systems specialising in NoCs, FPGAs, and high-speed interconnect. Former SVP Engineering at Achronix and VP Engineering at Arteris, with 11 years at Altera leading NoC tools and IP.