technology
Our technology is built ground-up with a software-first, data-driven system development approach.
Key Challenges
Growing Complexity
In order to support compute growth and energy costs, the computing paradigm is changing towards specialized compute solutions. This requires much higher integration and transition to chiplets for combining best in class systems. There is a substantial increase in complexity and risk.
Performance and KPI Guarantees
These specialized compute platforms needs very capable and yet very efficient data movement, which means more complex interconnect and the ability to analyze and guarantee performance, latency and other KPIs are becoming increasingly difficult. As you combine multi-chip solutions, this problem increases further.
Costs are Becoming Prohibitive
To hit these complex larger designs, the energy for processing and for data movement is increasing. The silicon footprint is growing, power is increasing which leads to increase cost of silicon and packaging.
Time to Market Window is Shrinking
The rapid acceleration of AI cycles is requiring designers to meet KPIs at first silicon.
How Baya Systems Addresses the Challenges
- Complexity
- Algorithm-driven, software-based design
- Scalable and modular IP for all fabric types
- Multi-level cache coherency
- Performance and KPI Guarantees
- Data-driven design with protocol customizability
- Deep static and dynamic microarchitecture analysis
- Granular control on fabric wire and logic
- Costs
- Unified fabric approach to reduce wire and area cost
- Workload optimization and post-silicon tuning in the same flow
- Reduced design time, analysis and development cost
- Time to Market
- Correct-by-construction to reduce risk and iteration
- Faster design closure and achievement of KPIs
- Implementation readiness for chiplets and scaling
Technology Overview
Intelligent software-driven, customizable, system IP solutions for efficient, yet unprecedented scale for SoCs and chiplets. Removes guesswork, reduces risk and cost of delivering complex high-performance systems.
Performance
& Scale
Performance & Scale
Hyper-efficient transport fabric that can deliver 4 TB/s throughput in a single cluster, and scale to multiple PB/s for multi-chiplet AI applications, and support advanced high-bandwidth memories.
Extreme
Flexibility
Extreme Flexibility
Unified
Efficiency
Unified Efficiency
Data-Driven Design
Data-Driven Design
Derisked
System
Derisked System
Modular
Implementation
Modular Implementation
Chiplet-Ready
Network
Chiplet-Ready Network
- Verifiable protocol-level cluster perimeter
- Performance and congestion isolation
Chiplet-Ready Cache Coherency
Chiplet-Ready Cache Coherency
- Multi-level cache coherent fabric IP
- Supports UMA, NUMA or sub-NUMA
Chiplet-Ready
Design Software
Chiplet-Ready Design Software
- Co-optimization of cache, memory, IO stacks
- Data-driven D2D analysis and optimization
Baya Systems Unified Fabric
The Baya Systems unified fabric provides a common transport supporting multiple protocols and coherency needs within a unified design flow. Physically-aware solutions can be optimized for power and area while delivering unprecedented performance, low latency and other key performance indicators (KPIs) from concept to deployment.
- Common transport optimizes performance and area
- Extensive flexibility in topologies and scale
- Correct by construction, deadlock free, QoS, RAS
- Workload-based, static global and local optimization
Optimizations
Baya Systems Benefits
Metrics
Current Market Challenges
Baya Systems Benefits
- Best Wire Efficiency
- Fabric channels in high performance silicon can take up to 20% of die area and power consumption
Up to 2x smaller fabric
vs standard mesh iso-performance
- Highest Bandwidth
- Performance bottlenecks created by protocol bridges, fabric transit points and longer routes
Up to 3 GHz and 32 PB/s
bisection bandwidth
- Lowest Latency
- Need for numerous protocol crossing bridges and scenic routes for communication flows
Lower latency
system and workload dependent
- Correct by Construction
- Deadlocks, QoS and tradeoffs unclear during design development
Up to 8 virtual channels
per network, deadlock-free, QoS built-in
- Future Proof Design
- Limited number of topologies, performance not scalable
8b-2048b channel width
with wide variety of topologies
- Fastest Design Closure
- Performance issues slow down architecture, complexity challenges slow down implementation
Data-driven design
and physically-aware implementation
