Data centers and high-performance computing (HPC) are the primary enablers of today’s power-hungry AI-driven technology, but chip designers, EDA vendors, and the data centers themselves have a long list of options available to them to help curb AI’s power consumption.

Chip designers play a critical role in ensuring energy efficient processing from the bottom up, whether that is hardware-software co-design techniques, optimized hardware and software architectures, better AI models and data management, or low power techniques. The fundamental problem is that power is a finite resource, and AI data centers are not considered essential users. Case in point: The state of Texas recently enacted a law allowing grid operators to turn off the power supplied to data centers when consumer demand is high.

But while power itself may be in limited supply, there is no shortage of options for reducing the amount of power needed to run AI. Some of those are recycled ideas, such as re-using the heat in district energy systems, which are underground networks of insulated pipes that can deliver hot water, steam, and chilled water to nearby buildings, or re-using old EV batteries. Other solutions are new, such as moving more compute to the edge or adding more granularity into power management at the chip level.