Baya Systems at the Heart of Open-Source Semiconductor Design and Data Movement

Home Blog Baya Systems at the Heart of Open-Source Semiconductor Design and Data Movement

Baya Systems at the Heart of Open-Source Semiconductor Design and Data Movement

by Brian Carlson

Introduction

Baya Systems was thrilled to attend the Andes Technology RISC-V CON in Silicon Valley on April 29, 2025, where industry leaders gathered to discuss the next frontier of semiconductor innovation. As more use cases demand modular, flexible architectures, RISC-V processors are gaining momentum 15 years on. At the conference, we engaged in deep explorations of how this open-source architecture is continuing to evolve and reshaping the landscape of system-on-chip (SoC) development, especially in applications like AI acceleration, 5G infrastructure, and low-power edge computing.

More importantly, the conference emphasized the importance of a comprehensive, collaborative ecosystem between different players in the industry to amplify successful semiconductor designs—something underscored by our own Dr. Eric Norige’s co-presentation with Imagination Technologies’ Pallavi Sharma, “Unleashing the Power of Heterogeneous Computing.” Our participation provided us a chance to not only offer solutions that address critical bottlenecks in data movement but also learn from our counterparts how we can better work together in harmony.

Here are our three key takeaways from the event that are shaping the future of semiconductor design:

1. RISC-V: Accelerating Innovation Across Industries

RISC-V adoption is growing astronomically due to the demand for custom processors capable of powering next-generation applications, such as AI-accelerated systems, deep learning, and 5G infrastructure. Since RISC-V is open-source, developers can more easily tailor processors for specific needs without running into the traditional roadblocks of closed architectures.

RISC-V’s ability to accommodate the needs of low-power edge AI, deep learning, and high-performance computing workloads makes it a transformative technology in a range of sectors—the agenda covered everything from deeply embedded networking to 5G infrastructure to AI scale-up and scale-out. Our CCO Nandan Nayampally presented how Baya Systems is “Empowering the Next Generation of Scalability” from closely-coupled processors and accelerators optimized in SoCs and chiplets for edge systems to data centers.

Watch the video of the presentation here.

To learn more, we invite you to download the presentation here.

2. The Critical Role of Data Movement in Modern SoCs

The challenge of data movement was a particularly prominent part of the conversation at RISC-V CON. At this point in time, modern SoC designs have the compute power necessary to perform even the most intensive tasks, such as AI and edge computing. So far, traditional designs with CPUs and GPUs managing data separately have been able to brute force past any limitations caused by that structure.

But as designs integrate multiple heterogeneous cores and chiplets, moving data efficiently, with both low latency and high bandwidth, is becoming a major bottleneck and resulting in non-optimal resource usage. Moreover, truly efficient data movement requires providing the necessary bandwidth and low-latency data to processors at the right time, which is key for real-time applications. Without it, even the most powerful processors are limited in their performance. With the conference’s focus on continuing to innovate on RISC-V processors, it was no surprise that data movement kept cropping up.

At Baya, we tackle this challenge directly with our WeaverPro™ CacheStudio software platform, which optimizes cache memory architecture to ensure smooth data movement between processors and memory, as well as our FabricStudio platform to create optimized, software-defined fabrics that are chiplet ready. Our solutions enable low-latency, high-bandwidth data flows for complex SoC designs, making sure the right data reaches the right processor without bottlenecks, helping SoC developers deliver high-performance systems that meet the demands of modern applications.

3. Collaboration Drives Ecosystem Success

A major takeaway from the Andes RISC-V Conference was the emphasis on ecosystem collaboration to make successful products. While RISC-V is adaptable to many use cases, it’s not a one-size-fits-all solution, and as the ecosystem grows, so does the need for cooperation across key players. To capitalize fully on the potential power of processors, GPUs, memory solutions, and interconnect fabrics, SoC developers must seamlessly integrate each component—and the producers of these components have a major role in making that possible.

Baya’s collaborations with Andes Technology and Imagination Technologies highlight how our combined efforts optimize heterogeneous designs. Andes provides RISC-V processors, Imagination supplies GPUs, and Baya offers the interconnect fabrics and software solutions that bring it all together. These kinds of joint efforts are vital for creating high-performance SoCs at scale.

The importance of working together as an ecosystem was clear throughout the event. RISC-V’s growth is dependent not only on processor development but also on how well the surrounding technologies and companies come together to address the needs of the developer community. At Baya, we understand that providing the right interconnect fabrics and software tools is essential to ensure smooth collaboration across the various pieces of the SoC puzzle.

Baya’s Presentation: Tackling Data Movement with Advanced Cache Memory Architectures

Baya’s presentation in conjunction with Imagination Technologies focused on optimizing heterogeneous core designs with advanced cache memory architectures. The session demonstrated how our WeaverPro™ CacheStudio software platform addresses data movement challenges in multi-core, multi-die chiplet designs by optimizing memory access patterns and improving interconnect performance. By enhancing cache architectures, we reduce latency and ensure that high-bandwidth data is fed efficiently to the processors. This is crucial for real-time applications that demand ultra-low latency and high throughput.

Download the Slides: Deep Dive into the Future of SoC Design

Baya’s presentations at the Andes RISC-V Conference offered valuable insights into the challenges facing semiconductor designers today, particularly regarding data movement and interconnect fabric solutions. Our session highlighted how Baya is uniquely positioned to support next generation designs with solutions that address these critical bottlenecks. To dive deeper into the technical details, we invite you to download the presentation slides here.

Explore our latest blog where we delve into system design strategies to overcome data bottlenecks in heterogeneous SoCs – read it now

What’s Next for Baya?

Baya’s participation at the Andes RISC-V Conference reinforced our commitment to being at the forefront of the next generation of semiconductor design, providing the tools and infrastructure needed to tackle the challenges of heterogeneous computing and data movement.

The future of semiconductors is centered around efficient, low-latency data movement across heterogeneous cores and chiplets, and Baya is leading the way in providing the interconnect fabrics and software tools that make this a reality. We are excited about the opportunities ahead and look forward to continuing to support the semiconductor ecosystem as we advance toward the next generation of high-performance SoCs.