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Revolutionizing Communication Architectures for the AI Chiplet Era: The Personal Journey Behind Baya Systems

The inception of Baya Systems was a profoundly personal journey for me, ignited by the explosive growth in demand for computational power in the era of artificial intelligence (AI). Watching AI and high-performance applications advance at an unprecedented pace, I couldn’t ignore the urgent need for more sophisticated communication architectures. Historically, data movement has lagged compute capabilities, and new trends have only exacerbated this problem, creating inefficiencies and bottlenecks. Having founded NetSpeed Systems, the first software-driven on-chip networks company to address this issue a decade ago, I was now witnessing a widening gap due to explosive growth in compute and a lack of progress in efficient data movement. This realization compelled me to join forces with key members of NetSpeed, Eric Norige and Joji Philip, to start Baya Systems. Our vision was to create semiconductor communication architectures that could meet the intense computational demands of modern applications while accelerating development cycles and enhancing performance and efficiency across a wide array of new semiconductor designs.
The Challenges of Scaling Computational Capabilities
As we delved into the challenges of scaling computational capabilities, we felt a strong sense of urgency as the communication bandwidth between compute, memory, and input/output (IO) emerged as a critical bottleneck. The existing system architectures, designed for single-chip and CPU-centric workloads, were simply not keeping up with the new AI paradigms that demand massively parallel and high-bandwidth data movement. This frustration fueled our determination to develop innovative communication and caching solutions at Baya Systems. It wasn’t just about solving a technical problem; it was about enabling seamless and efficient communication within computing systems to unlock their full potential. This mission became a personal crusade to push the boundaries of what was possible.
The trend of using chiplets to scale semiconductor designs introduces another layer of complexity to fabric and cache architecture. Chiplets allow the design of intelligent computing solutions by using the right mix of CPU, GPU, NPU, AI, and custom accelerators based on workload demands, resulting in the most optimal and power-efficient designs. They also accelerate time to market and improve yield and system cost. We found ourselves both intrigued and passionately driven by this trend and eager to tackle the additional challenges it brings. Legacy solutions designed for systems-on-chip (SoC) are falling short. We knew that new architectural ideas such as hierarchical namespaces, multi-level cache coherency, and latency-tolerant protocols were essential. With our extensive experience in designing successful fabric solutions at NetSpeed and transforming fabric architectures at Intel Data Center Products, we felt a deep responsibility to reinvent the communication and data movement architectures, driven by the emergence of AI and the chiplet era. This wasn’t just a professional goal; it was a personal commitment to innovation and excellence, aiming to create solutions that could meet the demands of next-generation compute systems.
A Phone Call that Changed My Course
A timely phone call from Jim Keller and Tanuja Rao finally helped us make the decision to leave my cushy job at Intel and return to the entrepreneurial world to build another foundational technology. Jim’s unwavering belief in me and the unique skillset of the core NetSpeed crew, and their extensive experience was incredibly motivating. His encouragement, along with the support from industry leaders like Stan Reiss at Matrix and Pat Gelsinger at Intel, gave us the confidence and resources to make this leap. Within a short span, we managed to secure investment, build a world-class team, acquire our first customer, and deliver a high-performance and unique solution. This rapid progress felt like a testament to our collective effort and commitment. Reflecting on this journey, I am personally overwhelmed with a sense of pride and excitement. Helping the industry overcome a critical bottleneck and being at the forefront of this transformative era feels like the most rewarding mission in my career.
Bio:
Dr. Sailesh Kumar is the founder and CEO of Baya Systems. Sailesh is a seasoned expert in SoC, Fabric, IO, Memory architecture, and algorithms, with over two decades of experience. He has pioneered several high-impact, industry-first technologies, including 400G Network Processor at Huawei, Software Defined Fabric at NetSpeed, Xeon Architecture Transportation at Intel, and Software Defined Chiplet at Baya. Sailesh founded NetSpeed Systems and served as its Chief Technology Officer until its successful acquisition by Intel. At Intel, as a Fellow, he initiated and led multiple projects, such as the design of a Xeon platform automation system and the standardization of data center compute protocols. Sailesh is also a prolific author, with more than two dozen highly cited papers and over 150 patents. He holds a PhD from Washington University in St. Louis and a B.Tech. from the Indian Institute of Technology Kanpur.