Powering Baya’s Next Phase:
New Expertise, New Milestones, Same Vision

Baya Systems is entering its next phase of growth powered by new expertise, proven leadership, and a continued commitment to excellence.

From achieving ISO 9001:2015 certification to expanding our leadership team and advisory board, to sharing insights at industry events and through new thought leadership pieces, in this issue we highlight the milestones that reflect our momentum and mission.

Together, these achievements reinforce Baya’s vision to deliver software-driven, chiplet-ready systems that enable scalable, efficient, and intelligent compute, from edge to cloud.

Quality Built-In: Baya Earns ISO 9001:2015 Certification

Baya Systems has achieved the globally recognized ISO 9001:2015 standard for quality management in less than five months. This milestone underscores our commitment to repeatable processes, customer-centric performance, and readiness to scale in the semiconductor industry.

Powering Baya’s Next Phase with New Expertise:
Meet our New Advisors & Executives

Baya Systems welcomes industry veterans Ty Garibay, Dr. Phanindra Mannava, and Kurt Shuler to its Technical Advisory Board, alongside new executives Ian Smythe (VP Product Marketing) and Kent Orthner (Principal Solutions Architect). Their collective experience in interconnect IP, chiplet-ready systems, and AI architectures reinforces Baya’s momentum toward redefining software-driven system design.

Baya & Tenstorrent Forge the Future of Compute Systems

We’ve teamed with Tenstorrent to demonstrate interoperability between our WeaveIP™ fabric and their TT-Ascalon™ processors,  and we also joined the Open Chiplet Atlas™ (OCA) ecosystem to enable truly composable, chiplet-ready compute platforms.

Whitepaper: Accelerating RISC-V Innovation with Baya & Tenstorrent

Our latest whitepaper with Tenstorrent explores how a co-architected RISC-V compute subsystem combining the Ascalon™ processor and Baya’s WeaveIP™ interconnect delivers exceptional scalability, flexibility, and power efficiency for AI and HPC workloads. The paper concludes that this joint platform can redefine subsystem design, accelerating time-to-market while reducing integration risk across chiplet and SoC architectures.

Baya Systems And Tenstorrent Licenses
Baya’s Sahana Barike Honored for
Outstanding Paper Presentation at SemiconTantra 2025

Congratulations to Baya Systems’ engineer Sahana Barike, who was recognized as a runner-up for Best Paper Presentation at SemiconTantra 2025. Her presentation highlighted the systemic limitations of conventional interconnect architectures in AI and HPC workloads and showcased how Baya’s advanced Network-on-Chip designs enable scalable, low-latency, and power-efficient data movement. This recognition underscores the depth of technical expertise within our team and our commitment to advancing the state of semiconductor innovation.

Blog: Inside AI Infra Summit 2025
Scaling Compute, Moving Data, Powering the Future

Our team was on the ground at the AI Infra Summit 2025 where it became crystal-clear that tomorrow’s AI infrastructure isn’t just about more compute, it’s about data movement at scale. From rack-scale switch fabrics pushing 10 PB/s bandwidth to open-standards chiplet ecosystems, the conversation is evolving fast. At Baya Systems we spotlighted how our software-driven, chiplet-ready fabric IP removes data-flow bottlenecks and empowers system designers across cloud, data-centre and edge.

Dr. Eric Norige Shares Startup Insights
at Synopsys Panel, AI Infra Summit 2025

At the recent AI Infra Summit 2025, Baya Systems’ Co-Founder and SW CTO Eric Norige joined Synopsys and other industry leaders on the panel “Building and Scaling an AI Chip Startup.” Eric shared Baya’s perspective on the critical role of efficient data movement, modular design, and software-driven fabrics in accelerating innovation for AI and HPC systems.

Latest Tech Threads Podcast Episodes
Episode 6: AI from Edge to Cloud: Hype vs Reality
In Episode 6 of TechThreads: Weaving the Intelligent Future, Nandan Nayampally sits down with Sally Ward‑Foxton (EE Times) and Dr. Ian Cutress (More Than Moore) for a candid discussion on the journey of AI across edge, cloud and everything in between. They tackle where the real bottlenecks in AI-system design are, dissect whether “edge AI” is delivering on its promise, and ask if GPUs still rule the roost. The conversation also delves into hardware–software co-design, open versus closed ecosystems, and the scaling realities of AI infrastructure.

You can now tune in to Baya’s podcasts on a variety of platforms, so you can listen wherever, whenever works best for you! Don’t miss out on the latest insights and conversations from the world of innovation.  

Upcoming Events

Join Baya & Tenstorrent for a Live Webinar on Scalable AI Systems

Don’t miss our upcoming webinar with Tenstorrent, where we’ll explore how software-driven fabrics and chiplet-ready interconnects are redefining AI subsystem design. Learn how combining Baya’s WeaveIP™ with Tenstorrent’s Ascalon™ processors enables higher throughput, lower latency, and faster time-to-market for next-gen AI architectures.

When: Nov 13, 2025

Where: Virtual – Live

Hear from Baya’s Experts at EETime’s AI Everywhere 2025

Baya Systems will join industry leaders at EE Times AI Everywhere 2025, a two-day virtual event exploring how AI is transforming data-center and edge architectures. Our experts will share insights on breaking data-movement bottlenecks, designing for performance-per-watt, and building scalable, chiplet-ready systems that power the next generation of AI infrastructure.

When: Dec 10-11, 2025

Where: Virtual

To stay updated on upcoming engagements and industry insights, subscribe to Baya Systems’ newsletter or visit the events page on our website.

Baya Systems in the News

News Spotlight

AiThority: Solving the Real Roadblock of Next-Generation AI

Newsroom

In this guest-article for AiThority, our CEO Dr. Sailesh Kumar dives into the hidden bottleneck in AI infrastructure: data movement. He highlights how today’s systems are hitting a “latency wall” not just because of compute limits, but because interconnects, memory bandwidth and modular architecture can’t keep pace with the scale of inference and training workloads. He argues that embracing open, chiplet-based fabrics, re-thinking crossbar limits and supporting software-driven IP are key to democratizing AI innovation and sustaining next-gen models.

Join our Team

We are hiring! With rapid growth, we’re expanding our engineering (software and hardware) and commercial teams. We encourage you to explore opportunities and join the team.

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